The development and production of integrated circuits (ICs) follows a multistage process beginning with the logical design phase. At this stage, engineers describe circuit behaviour on the register transfer level (RTL) using hardware description languages such as VHDL or Verilog. These descriptions specify how data moves between registers, as well as the logical operations performed on that data. A synthesis process then translates the RTL description into a network of fundamental logic gates like AND, OR, NOT and storage elements such as flip-flops.
Following logical synthesis, the physical design stage creates a layout-level representation of the circuit, commonly referred to as the gate-level netlist. This includes defining the component floorplan, placing standard cells and arranging the detailed routing of interconnections between transistors. Since this layout employs fabrication-specific libraries and timing models, the physical design is tightly coupled to the targeted manufacturing technology. For example, even a simple HDL command like “wait for 10 cycles” will be implemented differently depending on the foundry’s internal logic and simulation infrastructure.
Before manufacturing can commence, a series of physical verification steps ensures that the layout satisfies process constraints. This includes design rule checks (DRC) to enforce geometric constraints and layout versus schematic (LVS) verification to confirm consistency between circuit connectivity and intended logical behaviour. These checks are specific to each fabrication process and seldom transferable across foundries. Once the layout passes verification, the final dataset is delivered to the manufacturer in a procedure known as tape-out.
The fabrication process builds the IC layer-by-layer on a wafer—typically a high-purity silicon disc. Using photolithography, patterns are transferred onto the wafer by applying photoresist and selectively exposing it to ultraviolet light; the exposed regions are then chemically developed to create highly precise patterns of conductive and insulating material. After all layers have been processed, the wafer is diced into individual dies. Each die is mounted onto a package substrate (bonding) and enclosed in a protective housing, resulting in the finished integrated circuit device.
Throughout design and fabrication, optimisation focuses on three key criteria: meeting timing constraints, minimising silicon area, and reducing power consumption. The circuit must operate correctly within a specified clock frequency, requiring careful control of signal propagation delays across logic paths. Silicon area is a precious resource, so compact layouts that maximise die count per wafer are economically advantageous. Power efficiency is equally critical, particularly for mobile and embedded applications, and techniques such as clock gating—which disables inactive portions of the circuit—are commonly used to curb unnecessary switching activity and reduce energy usage.