ARM features classified

The new ARM features can be categorized into two main groups, each addressing distinct aspects of ISA (Instruction Set Architecture) functionality and design.

The program flow related functionality

The first group encompasses program flow related features, which operates primarily at the CPU core level, affecting the memory management unit (MMU) and cache hierarchy. These features directly influence the feature programmers, compiler settings and finally the resulting program flow of the feature itself. 

For instance, ARM’s Memory Tagging Extension (MTE) is a significant innovation within this group. MTE operates through the MMU and cache hierarchy, enhancing debugging and runtime memory safety. By detecting potential memory safety violations, it can trigger predefined actions such as logging incidents or terminating processes. 

// Allocate memory and set a tag
void *buffer = malloc(64);

// Assign tag 0x3 to the memory region
mte_set_tag(buffer, 0x3);      
char *ptr = buffer;

// Assign the same tag to the pointer
mte_set_pointer_tag(ptr, 0x3);  

// Tags match: Access allowed
ptr[0] = 'A';   
   
// Unsafe access (out-of-bounds): Fault raised
ptr[80] = 'B';  

// Free memory
free(buffer);

While MTE serves to prevent memory safety issues, its implementation introduces notable changes to control flow, creating additional software variants, increasing demands on quality management, and ultimately contributing to technical debt.

Other examples of ISA-related features include:

• Branch Target Identification (BTI): During execution, the processor verifies whether an indirect branch or jump targets a valid BTI-marked location. If it does not, the processor halts execution or traps the error.
• Pointer Authentication (PAC): PAC employs cryptographic keys stored securely within the processor (e.g., in hardware registers). It appends a Pointer Authentication Code to pointers and validates their integrity during execution, protecting against unauthorized modifications.

The supervision related functionality 

The second group consists of features that rely primarily on CSRs (Control and Status Registers). These registers enable configuration, control and monitoring of hardware mechanisms, particularly for managing multi-tenant performance. The program flow of a specific feature is less to not impacted. Here a supervisor e.g., hypervisor for VM or operating system for processes inject the necessary control.

Note: To be clear, the CPU cores also have to do processings based on the register values, but the technical realization primarily involves many other components. 

A key example is MPAM (Memory Partitioning And Monitoring), which provides resource partitioning and monitoring capabilities for shared resources like caches, interconnects, and memory bandwidth in ARM-based systems-on-chip (SoCs). 

MPAM, introduced in the ARMv8.4-A architecture, is implemented in components such as L3 caches, DRAM controllers and interconnects to enforce quality-of-service (QoS) policies and monitor resource usage.

MPAM is designed to enable fine-grained control over system resources in multi-core systems. Its functionalities include:

• Partitioning: Allocating memory and cache resources to specific processes, cores and/ or virtual machines (VMs). Most configurations can be made via EL1 register. 
• Monitoring: Tracking resource usage, such as memory bandwidth consumption, to facilitate system profiling and optimization.
• Enforcement: Preventing resource starvation by ensuring fair allocation and predictable performance across workloads.

Key components involved for MPAM:

• L3 Cache (DSU): Segments shared cache (e.g., L3) into partitions for different cores or tasks. Usually per core cluster. 
• Interconnect (Coherent Mesh Network, short CMN, as part of ARM’s CoreLink product family): Enforces QoS policies, controlling memory bandwidth and traffic prioritization.
• Memory Controllers: Allocates memory regions and enforces bandwidth quotas based on MPAM policies.
  • Accelerators (GPUs): Tags traffic to manage their impact on shared resources.
    • Peripherals (I/O): Regulates peripheral access to shared system memory and bandwidth.
      

Note: Memory controller is not MMU.

• The Memory controller is responsible for managing physical access to the computer’s memory (RAM). It acts as the interface between the CPU and the physical memory.
• The MMU is responsible for virtual memory management and translates virtual addresses (used by software) into physical addresses (used by hardware).