WebAssembly and RISC-V are two new Instruction Set Architectures (ISAs). WebAssembly uses a stack machine model (Van Neumann Architecture), while RISC-V, like most hardware architectures, uses a register machine (Harvard Architecture). However, the line between bytecode and actual hardware instructions is not always clear:
- There are also experimental hardware implementations of WebAssembly (WASM), which you can find at this URL: WebAssembly Hardware Implementation.
- Conversely, people are using RISC-V in contexts where WebAssembly is typically used, such as for smart contracts on blockchains. You can see an example of this at the following URL: RISC-V for Smart Contracts.
Feature comparison as of this article here, transferred and extended from image to markdown:
| WASM | RISC-V | |
| Open source | Yes | Yes |
| Memory architecture | Load/Store | Load/Store |
| Floating point | Yes | Yes, but in extension |
| SIMD(“Single Instruction, Multiple Data”). It is a type of parallel processing technique used in computing to perform the same operation on multiple data elements simultaneously. | Yes | Yes, but in extension |
| Separate code and data | Yes, because of stack machine | No, because of register machine |
| Pointer width | 32 bit | 64 bit |
| Maximum data width | 32 bit | 64 bit |
| Typing | Weak | No |
| Control flow | Restricted. Any potentially harmful code is blocked and logged, ensuring the security of the execution environment. This is no longer valid because of the component model. Due to “bytecodealliance”: In the component model, these type definitions are written in a language called WIT (Wasm Interface Type), and the way they translate into bits and bytes is called the Canonical ABI (Application Binary Interface). A Wasm component is thus a wrapper around a core module that specifies its imports and outputs using such Interfaces. | Arbitrariy |
| Memory model | linear | paged |
| Memory protection | No | RWX |
| Synchronization primitives | CAS. CAS is widely supported by modern processors and is the basis for many lock-free and wait-free algorithms. | LL/SC. It’s typically used in hardware or low-level programming contexts. |
| Execution image | WASM | ELF |